Matrix-type display devices, such as capacitive flat matrix displays, liquid crystal displays, and plasma displays, share similar peripheral mechanism for voltage application and its control, although they differ from each other in materials used for display elements and voltages supplied to display panels. A schematic arrangement of a capacitive flat matrix display is illustrated as an example in a block diagram constituting FIG. 7. As disclosed in Japanese Laid-Open Patent Application No. 60-95495/1985 (Tokukaisho 60-95495; published on 28 May, 1985), a display panel (EL panel) 71 of a capacitive flat matrix display shown in FIG. 7 includes: an electroluminescence element (hereinafter, will be referred to as an EL element) as an light emitting layer; transparent electrodes provided as data electrodes 71a on one of two surfaces of the EL element; and backside electrodes provided as scanning electrodes 71b on the other surface of the EL element. A pixel is formed at every crossing point of the data electrodes 71a and the scanning electrodes 71b, so the display panel 71 has pixels arranged in a matrix form.
A scanning driver 72 is connected to the scanning electrodes 71b, supplying predetermined voltage to the scanning electrodes 71b through operation of a shift register circuit 73. A data driver 74 is connected to the data electrodes 71a, supplying predetermined voltage to the data electrodes 71a through operation of a shift register and latch circuit 75. A drive circuit 76 includes a write drive circuit 76a and a modulation drive circuit 76b and produces a high voltage for the display panel 71 from voltage, VD, (for example, 12V) for use in a drive circuit supplied from a power source 80 according to a control signal input from a drive logic circuit 77. The write drive circuit 76a supplies write voltage (for example, 200V) to the scanning driver 72 which then supplies the voltage to pixels illuminate the display panel 71. The modulation drive circuit 76b supplies modulation voltage (for example, 40V) to the data driver 74 which then turns on or off the EL elements according to display data.
The drive logic circuit 77 produces timing signals (control signals) 78 and 79 to drive the display panel 71 from voltage, VL, (for example, 5V) for use in a logic circuit supplied from the power source 80 according to display data D and input signals including clock signals CK for display data transfer, horizontal synchronous signals H, and vertical synchronous signals V. The data (digital data) to produce the timing signals 78 and 79 is stored in an internal ROM (Read Only Memory) 77a. The timing signal 78 is used to control the timing of the write voltage supply from the write drive circuit 76a. Meanwhile, the timing signal 79 is used to control the timing of the modulation voltage supply from the modulation drive circuit 76a. 
FIG. 8(a) and FIG. 8(b) show a control signal production circuit 81 for write drive provided inside the drive logic circuit 77, a timing chart of its control signals, and a waveform of a write drive voltage supplied to the display panel 71. As shown in FIG. 8(a), The ROM 77a provides four control signals W1 (write 1), W2 (write 2), D1 (discharge 1), and D2 (discharge 2) as parallel data for transistor control. Then, as shown in FIG. 8(b), the control signal W1 rises first among the four control signals to charge from 0V to 100V (first charge). The control signal W2 subsequently rises to charge form 100V to 200V (second charge). When being charged to 200V, the EL element luminesces. When the EL element is to be turned off, the control signal D1 rises to discharge from 200V to 100V (first discharge). The control signal D2 subsequently rises to discharge from 100V to 0V (second discharge).
In a conventional control signal production circuit 81, as detailed in the above, the ROM 77a stores all the data required to drive the display panel 71 for each kind of control signals and therefore needs a large storage capacity. For example, in the case illustrated in FIG. 8(a) and FIG. 8(b), the ROM 77a must store all the data representative of “high” and “low” level sections of each of the control signals W1, W2, D1, and D2. Besides, since the ROM 77a provides parallel data for each of the control signals, an increased number of output lines are required to transfer a large amount of data per unit time. For these reasons, the conventional control signal production circuit 81 has problems including overgrown dimensions and cost of the ROM 77a due to too large an amount of data, increases in the wiring area to enable parallel transfer of data and also in the substrate area.